Single diffusion break (SDB) devices are becoming more desirable due to their improved performance capabilities. However, the present performance of such devices is mainly affected by the resulting shape of the epi source/drain regions. This shape impacts contact resistance, device drive current and leakage current.
As shown in FIG. 1A, a prior art device 10 includes a dummy gate 12 covering a shallow isolation trench 14 between a pair of neighboring FinFETs 16A, 16B (each only partially shown) providing a single diffusion break. Prior art device 10 is also shown with an epitaxial source/drain (S/D) region 18 (for FET 16A) and S/D region 20 (for FET 16B) formed within a substrate 22. Spacers 24 are formed along FinFETs 16A, 16B and the dummy gate 12.
However, patterning for the shallow isolation trench 14 is difficult at small dimensions using conventional lithography and etch techniques presently available. The prior art device 10 may suffer from leakage between the S/D through the dummy gate 12. Also, as shown in FIG. 1B, after cavity etching, the epitaxy (epi) of the S/D regions 18, 20 grows non-ideally resulting in asymmetric growth and a shape that degrades performance. This growth typically results in a slanted epi S/D region slanting downward toward the isolation trench 14 because there is little (if any) substrate 22 available for growth adjacent the isolation trench 14. Because of the small dimensions, the cavity etch for the S/D regions etches away most of the substrate 22 near the isolation trench 14. In addition, the device 10 still provides a potential leakage path through the dummy gate 12.
To alleviate some of these issues, a different trench isolation structure (and methods of manufacture/fabrication) has been proposed that enables a growth of more uniform epitaxial S/D regions to improve active device performance. Such structure and methods for manufacture/fabrication are detailed in U.S. patent application Ser. No. 15/195,988 entitled “Novel STI Process For SDB Devices” and filed on Jun. 28, 2016. One purpose or benefit of the structure(s) and process(es) described in that US patent application is to protect from, or reduce, silicon loss in the SDB structure during epitaxial cavity etch next to the STI region.
In addition to the foregoing issues of the prior art SDB FinFET device(s), when both SDB FinFET devices and double diffusion break (DDB) FinFET devices are fabricated on the same chip, it is desirable to match closely the Fin heights of the two types of devices. When utilizing an anisotropic etching process (or at least partially anisotropic process) for the Fin reveal process, including a two-step process such as etching and chemical oxide removal (COR), this results in a relatively wide recess in the silicon (and the Fin is recessed at the edges), a taller raised STI region, and shorter Fin height (silicon loss from top of fin, e.g., on order of 10 nm) and rounded Fin top.
The wider silicon recess and raised STI height degrade the aspect ratio (AR) in the SDB structure. In addition, the recessed edges of the Fin structure may result in big facets in the source/drain (S/D) region, thereby causing a weaker junction and contact landing problems. Having a short Fin height leads to weaker device performance, and may cause problems when seeking to match Fin heights between SDB structures and DDB structures.
Accordingly, there is a need for a new trench isolation structure (and methods of manufacture/fabrication) that reduces S/D facets and AR degradation in SDB structures. Reducing S/D facets and improving AR in SDB structures can be accomplished by smaller silicon recess widths, shorter raised STI heights, increased Fin heights and/or flatter Fin tops, thereby resulting in improved device performance.